1.1.8 - CPU: Control Unit and ALU.
To define a computer system, one must understand computer organization and computer architecture, two distinct but connected concepts:
- Computer Architecture: Defines the fundamental properties of hardware components and their interconnections to achieve specific performance and functional goals. Key elements include data representation, I/O protocols, and instruction sets.
- Computer Organization: Involves the design and physical arrangement of various hardware components to meet the goals specified in the architecture. Different models can exist for a given architecture based on factors like cost, size, and technology used.
2. Central Processing Unit (CPU)
The CPU is the "brain" of the computer, responsible for processing data and managing other system components. A typical CPU undergoes four phases for its primary functions:
- Fetching instructions from memory.
- Decoding instructions to determine the required operations.
- Executing the instructions.
- Storing results back into memory.
These four phases are known as the CPU cycle, which includes subsystems like the Arithmetic Unit (AU), Logic Unit (LU), and Control Unit (CU). The CPU also utilizes memory subsystems such as Main Memory, Cache Memory, and Memory Registers for processing tasks.
3. Arithmetic Unit (AU)
The AU is responsible for performing arithmetic operations (addition, subtraction, multiplication, division). Some CPUs have separate AUs for integer and floating-point operations. The AU receives instructions that include:
- Opcode: Specifies the operation to be performed.
- Operands: Data on which the operation is to be performed.
- Format Code: Indicates the operand format (e.g., fixed-point or floating-point).
4. Logic Unit (LU)
The LU handles logical operations, using gates like AND, OR, and NOR. It performs operations such as comparisons (greater than, less than, equal to) and bitwise shifts (left, right).
5. Control Unit (CU)
The CU directs the flow of data within the CPU, fetching instructions from memory, decoding them, and signaling the AU or LU to perform specific tasks. It uses various registers, including the Program Counter (PC) and Instruction Register (IR), to manage the order of execution.
6. Memory Subsystems
6.1 Main Memory Unit
Main memory, or RAM, is the primary storage for data and instructions currently in use. It is volatile, meaning its contents are lost when the computer is powered off. The amount of RAM influences the system's speed, as more RAM allows more instructions to be stored and accessed quickly.
6.2 Cache Memory
Cache memory is a smaller, faster type of memory that provides rapid access to frequently used data. It comes in two levels:
- Primary Cache (L1): Located within the CPU, it offers the fastest access.
- Secondary Cache (L2): Located on the motherboard, it is larger but slower than L1 cache.
6.3 Registers
Registers are temporary storage locations within the CPU that hold instructions, data, and intermediate results. Key types of registers include:
- Program Counter (PC): Holds the address of the next instruction.
- Instruction Register (IR): Stores the current instruction.
- Memory Address Register (MAR): Holds the address of the memory location to be accessed.
- Memory Buffer Register (MBR): Holds data transferred to/from memory.
- Accumulator (ACC): Holds results from arithmetic and logic operations.
7. Internal Communications
The CPU communicates with memory and I/O devices through two main types of internal communication:
- Processor to Memory Communication: Uses MAR and MBR registers to read/write data from/to memory locations.
- Processor to I/O Devices Communication: Uses an interface unit to manage data transfer between the CPU and I/O devices.
7.1 Processor to Memory Communication
This involves reading and writing data to memory. For reading:
- The CPU loads the memory address into the MAR.
- A READ signal is sent via the control bus.
- Data from the specified address is loaded into the MDR.
- The CPU receives the data.
For writing:
- The CPU loads the memory address into the MAR and data into the MDR.
- A WRITE signal is sent.
- Data in the MDR is stored at the specified memory address.
7.2 Processor to I/O Devices Communication
Communication with I/O devices is managed via an interface unit that interprets CPU commands for device controllers. This involves operations such as I/O read (data transfer from input device to CPU) and I/O write (data transfer from CPU to output device).